ChipFlow’s Vision: ASICs for the Many, Not the Few
Key takeaways
Untapped Market of 50,000+ SME OEMs - and ChipFlow Is the First to Truly Unlock It
ChipFlow’s Core SME ASIC Design Platform - and Becoming the Channel for That Moves the Industry (for complementary offerings)
Aligned with Strategic Public Capital - EU Chips Act Consortium Momentum
Early Market Traction - Through Strategic Partnerships and Real-World Pilots as needed for soon to open Seed stage round
Scalable Revenue Model with Strong Expansion Potential from H2 2026 Onward - Strongly supported by EU Chips Act Design Enablement Team (DET) position
We are building an open, accessible IC design platform tailored for SMEs, combining pre-verified reference designs, support for both open-source and proprietary tools, and a fully integrated supply chain. Our platform is already enabling pilot projects with SME and academic partners and will be further expanded through our joint EU Chips Act application with a leading EDA vendor and ChipCraft. This effort aims to create a step change in how SMEs approach silicon design, making the process faster, more affordable, and significantly less risky. As part of this, we aim to reduce not only technical barriers but also economic and operational ones. These are challenges that would otherwise take SMEs years to navigate alone.
What follows is the rationale behind our platform, the market gaps we’re addressing, and how we’re laying the groundwork for the next wave of silicon innovation. This next wave will be driven not by scale, but by specificity and imagination.
We’re entering a new era, one where general-purpose chips are giving way to specialised silicon in an increasing manner. While general-purpose chips still represent the lion’s share of the €400–600 billion semiconductor market, application-specific chips (ASICs) are increasingly viewed as a strategic advantage for OEMs with differentiated needs. While this market figure underlines the sheer scale of the opportunity, it is important to note that our TAM is a specific and unique subset of this space — SMEs who are currently shut out of ASIC design.
More than 50,000 SME OEMs around the world stand to benefit from this shift, but the path to custom silicon remains gated, costly, and overly complex.
At ChipFlow, we think it’s time for a new approach. One that opens up ASIC innovation to more than just the usual players. Our mission is to democratise chip design, giving access to SME OEMs, startups, and others who’ve traditionally been left out of the silicon game. We started our journey by building a purpose-built IC design platform with pre-integrated Supply Chain enabling cheaper and easier chip design. However, we have learned along the way that there are even further ways we can better enable the market. In particular, we are explicitly focused on building a fully integrated supply chain with trusted partners. This is a critical enabler for new, smaller users, as it dramatically shortens their ramp-up time and removes costly missteps.
The Silicon Gap: A Market Hiding in Plain Sight
Right now, most semiconductor innovation happens at the top: hyperscalers, big tech, major corporations. ASIC design remains a walled garden, locked down by a few dominant EDA vendors, expensive licenses, obscure IP licences, and high minimum production thresholds.
But below that top tier is a huge, underserved market. We estimate more than 50,000 SME OEMs are building products with general-purpose chips when what they really need is custom silicon.
What’s holding them back? It’s not lack of ideas or need, it’s lack of access. They don’t have the tools, the foundry relationships, or the time and money to tackle traditional ASIC workflows. And they’re not looking for the next 3nm bleeding edge chips. They need chips that are right-sized, cost-effective, and purpose-built for their products. For the majority of SME OEMs, we’re talking about ‘legacy’ node ASICs. Design processes that are proven, robust, and able to be manufactured with lower volume constraints.
General-purpose processors are often too big, too power-hungry, too pricey, or simply just overkill for what’s needed.
ChipFlow: Built for the Long Tail
We created ChipFlow to serve this long-ignored segment. Our initial focus on lowering the IC design tool costs through our platform significantly reduced the SME OEM entry barrier for ASICs. However, we can lower the barriers more by incorporating pre-verified reference designs. These make ASIC designs even cheaper, faster, and dramatically more accessible. After establishing a solid open-source-driven IC design platform with a focused set of technology choices, we are expanding to include more open-source components and also support for proprietary tools and IP. This provides SME OEMs access to a proven set of tools and IP, no matter what their ASIC design needs are. This dual approach makes ChipFlow uniquely positioned. We are not just a toolkit for hobbyists or research projects, but a complete, professional-grade platform built to scale with SME ambitions.
Open by Default…
We build on, and contribute to, the open-source EDA ecosystem. That means no licensing friction, full transparency, and European control over critical design infrastructure. We are pledging our platform to be a test bed for the EU Chips Act-driven €50 million program to push open-source EDA tools across the board. This includes creating a stable 22/28nm digital design flow.
We believe this effort not only strengthens the ecosystem, but also positions ChipFlow at the heart of a critical transformation in European semiconductor independence.
… also to Proprietary Vendors
We are adding support to our platform to act as a channel for our strategic partners to offer their offerings. This includes an EDA tool vendor and selected IP vendors. This mixed offering gives SME customers the best of both worlds. They can choose what suits their design needs best, all integrated through our platform which makes it significantly easier to engage with ASICs.
Reference Designs
To help SME OEMs accelerate time to market and reduce design risk, ChipFlow offers pre-verified, reusable SoC templates tailored to common application needs. These are not just demonstration designs. They are production-ready baselines that can be customised with specific IP, analog components, or peripheral integrations. Many SMEs are driven by a core innovation, often an algorithm or domain-specific function, and need to translate that into silicon much faster than traditional ASIC design timelines allow. Our reference designs address this by providing 80 percent ready solutions from the outset. The first of these are Remote IO controllers for Automotive and Industrial IoT, with more designs being developed based on customer demand. In addition, our platform is open to contributions from strategic IP partners, allowing them to build and publish their own reference designs directly into the ecosystem.
Verilog or Python (or AI!)
We support both traditional Verilog and Python-based design flows, giving teams the flexibility to work the way they know best. Our goal is to enable SMEs, and the reality is that a majority of open-source EDA efforts are based on the more traditional languages and simulators. Further, AI is making fast progress across the board, including in semiconductor design. We at ChipFlow are working on our own agents and also engaged in selected dialogues with potential future partners. We might see design entry languages becoming based on common English language, but more importantly, we plan to ensure ChipFlow remains a proactive enabler in that transition.
Integrated Supply Chain
We continue to provide SME OEMs direct access to the ASIC supply chain via our partners, with many new such partners joining recently. Our platform bridges the entire flow from design to tape-out by integrating proven partners, streamlining handoffs, and removing friction around packaging, IP sourcing, and manufacturing. This is especially important for first-time ASIC users. Without these integrations, learning the ropes would take years and substantial capital.
We are super excited about our new, increased offering to SMEs. We hope it will enable thousands of previously blocked-out OEMs to start exploring ASICs.
It Is All About Momentum and Timing
Building access to a new market segment takes time, especially in an industry as complex as semiconductors. The past few years have been about building the basic platform and ensuring it has a strategic market fit.
The first major step in starting to push our expanded offering out will be a joint EU Chips Act DET application. In this, ChipFlow partners with a leading EDA and analog design house experts ChipCraft. The consortium brings together a unique European design offering targeted to SME OEMs. If successful, this initiative will not only provide funding and strategic visibility, it could also give ChipFlow early access to customers, pilot programs, and infrastructure investments. This would accelerate our time to market and expand our influence within the European semiconductor ecosystem.
The EU Chips Act subsidised program will kickstart SME OEM demand for ASICs in a manner not seen before. ChipFlow, together with its consortium partners, will be among the key players to enable and benefit from the change.
Beyond the DET-enabled market, ChipFlow is benefiting from increasing customer signals, with several hardware SMEs and academic parties running pilots on the ChipFlow platform. These collaborations give us the market validation needed for our seed funding round later this year. We track engagement and success using key performance indicators such as design starts, IP module reuse rates, time to prototype, and partner onboarding velocity. These metrics help both us and our investors measure impact and fine-tune growth.
The plan remains to have our platform operational and ready to scale from the second half of 2026, well aligned with the Chips Act DET timelines.
At ChipFlow, we are not just making chip design possible.
We are removing every major barrier to entry — economic, technical, and ecosystem — and making custom silicon a feasible, repeatable, and scalable path forward for thousands of innovative companies.
