ChipFlow Expands RTL Language Support and adds paid tier offering
ChipFlow was created to make chip design accessible to a much broader audience. What started as a focus on cloud based open-source EDA and Python-based design tools is now growing into something larger. We are expanding our platform to support a wider range of users—from hobbyists and academics who are learning and experimenting, to companies building production-grade silicon. Our platform now offers two complementary RTL design options tailored to different needs, while staying true to our original mission of lowering barriers to chip design.
Introducing the Traditional HDL Flow
For commercial users, different requirements come into play. Integration with proprietary PDKs, access to IP libraries, and adherence to industry-compliant flows are critical for getting a chip from concept to production. To meet those needs, we are introducing support for Verilog, and eventually SystemVerilog. This addition, together with Verilator support, provides the tools and support needed for a wider range of projects, including professional-grade, full production volume designs.
The additions, together with the recently announced reference designs, enable ChipFlow users to test their design ideas using the existing ‘free to use tier’ with its openPDK integration, and to grow into more commercially minded projects with proprietary PDK support using the paid, commercial tier.
Two Flows, One Platform
ChipFlow has also been trail-blazing to lower the barriers of chip design. This is now possible through our ‘Free to Use’ tier with pre-integrated open PDKs enabling users to test their design ideas without having to pay or sign NDAs. This is ideal for academics, hobbyists, and early-stage innovators who want to explore and prototype quickly.
For those with more specific design needs, ChipFlow is introducing a paid tier which provides the possibility to design proprietary designs and to benefit from proprietary IP, Reference Design and access to proprietary PDKs. Together with ChipFlow provided technical support, this tier is ideal for for commercial teams, startups, and companies scaling toward mass production.
While these flows serve different communities, they are both part of one unified platform. Both tiers are fully supported, continue to evolve, and give users the freedom to choose the path that best fits their needs. Please note that ChipFlow is further engaged in plans to provide a 3rd tier aimed at heavy duty commercial users - more information on this in due course.
Open-Source Commitment in Action
Our recent partnership with ChipFoundry demonstrates how serious we are about keeping chip design open and accessible. By linking ChipFlow’s open-source EDA tools directly with ChipFoundry’s fabrication portal, we now provide an end-to-end ASIC workflow—from RTL to tapeout—that is lightweight, license-free, and available to anyone who wants to take their design to silicon, all in an inexpensive package. We are looking to add further open-source led community support still later this year.
Looking Ahead: The (AI driven) Future of HDLs
We believe the future of hardware description languages is changing quickly. AI-driven HDLs that can translate natural language prompts into synthesizable hardware descriptions are on the horizon. These tools could completely redefine how hardware is specified and built. Amaranth, with its Pythonic interface and flexibility, is well positioned to act as a bridge into that future, making it easier to integrate with emerging AI-based design workflows. This area is an interesting emerging area and thus if anyone is interested to collaborate in the area - we’d love to hear from you and your plans!
