AI Makes Chip Design Easier. But Tapeout Still Takes Experience.

Chip design is becoming easier to access, and that is a very good thing.

Open-source EDA has come a long way. AI can already help write RTL, generate scripts, inspect logs and automate repetitive work.

Someone can go to GitHub, pull down serious design tools and start building a flow. OpenROAD, Yosys, Verilator, xschem, KLayout and others have made serious design work possible without starting with a full commercial stack. The remaining limitation is PDK access: only a small number are genuinely open, and more foundries need to follow.

AI is lowering the barrier again. Smaller teams can now do things that once required much more infrastructure and budget.

The barrier to entry is falling faster than the barrier to tapeout.

A flow that runs is not the same as a flow you trust

Most ASIC projects do not get into trouble because the flow will not run. They get into trouble when the results start needing judgement.

Synthesis runs, but timing is poor. Place and route completes, but congestion is difficult to resolve. Verification passes in one environment and fails somewhere else. A warning looks harmless until it becomes a problem later.

The closer a project gets to tapeout, the less useful it is to simply know that a tool completed successfully. Somebody needs to understand whether the assumptions are sound and whether the result can actually be trusted.

A clean report is useful. Knowing whether you should believe it is more important.

The bottleneck is moving from tools to experience

Open-source EDA is often discussed in terms of cost, and that remains a big part of its value. But as access to capable tools improves, the shortage of experienced engineers becomes more visible.

You can install a toolchain in an afternoon. You cannot install ten years of tapeout experience.

More teams can now start ASIC projects and make meaningful progress, but that does not mean they have the experience needed to get through verification, signoff and manufacturing.

This matters particularly for teams coming into ASIC development from software, embedded systems or board-level hardware. Strong engineering experience does not automatically translate into deep knowledge of physical design, PDKs, signoff or working with a foundry.

AI helps most when somebody knows what good looks like

AI will make experienced engineers much more productive.

It can already help build scripts, inspect reports, summarise logs and remove tedious work from the flow. As agents become more deeply integrated into EDA environments, those gains should increase.

But AI can also produce convincing answers that are wrong. It can generate RTL, suggest a timing fix or recommend a change to the flow. Somebody still needs to judge whether that answer makes sense.

AI can save hours. It can also help you get to the wrong answer faster.

That matters because ASIC mistakes get more expensive the further they travel through the flow. A bad software release can often be patched. A bad tapeout is already in silicon, and the cost of getting it wrong rises sharply on more advanced processes.

The value of an experienced engineer is often not that they know how to run the flow. It is that they know which problem is real, which warning can wait and which apparent fix will create another problem later.

AI makes open tooling even more interesting

AI agents need to inspect logs, modify scripts, call tools and check outputs. Open tooling is well suited to that kind of workflow because it is transparent and scriptable.

That does not mean commercial EDA disappears. Verification, implementation and signoff will continue to rely heavily on commercial tools. The likely direction is mixed flows combining open-source tools, commercial EDA, internal automation and AI agents.

The important question is whether teams can make all of those pieces work reliably together.

Experience is becoming harder to ignore

We recently asked our network what they saw as the biggest bottleneck to ASIC tapeout in 2026. Finding the right engineers came out ahead of verification and signoff, EDA cost and design flow.

That matches what we hear across the wider ecosystem.

AI and open-source EDA will make chip design more accessible. Smaller teams will be able to do more, and companies that could never justify a large internal ASIC organisation may be able to develop custom silicon with much leaner teams.

That is exactly the direction the industry should be moving in.

Open-source EDA has made it easier to start. AI will make it easier to move faster.

The challenge is having the experience to finish.